1. Field of the Invention
The present invention relates to a data processor capable of processing a conditional branch instruction, and more specifically a control circuit used in a central processing unit for processing a conditional branch instruction.
2. Description of Related Art
Recent central processing units have adopted an instruction prefect control for a speed-up of a processing. In addition, a pipelined processing, in which a processing required for executing one instruction is divided into a plurality of processings, which are executed in parallel at one time, has been also adopted so as to rapidly process a given sequence of instructions.
However, advantages of the instruction prefetch and the pipeline processing cannot be often obtained when a conditional branch instruction is executed. The reason for this is as follows: Assume that a conditional branch instruction is prefetched and an branch destination instruction or a next instruction in the case of no branching are prefetched so that a pipeline processing is performed. In this condition, if a branch condition for the conditional branch instruction is determined or decided on the basis of the result of execution of a preceding instruction, it is in some case that the result of the processing becomes invalid after the conditional branch instruction.
More specifically, when a conditional branch instruction is executed, a conditional branch instruction is prefetched in a prefetch unit, and then, a branch destination or an instruction next to be executed in case of no branching is accumulated in the prefetch unit. On the other hand, after an instruction decoder decodes a conditional branch instruction supplied from the prefetch unit, the instruction decoder decodes the instruction next supplied from the prefetch unit. If the next instruction includes a memory operand, the instruction decoder sends an address generation information to an operand address generator. At this time, if execution of a preceding instruction before the conditional branch instruction has not yet been completed and if the condition for branching depends upon an execution result of the preceding instruction, there is possibility that the address supplied from the operand address generator is not executed. The operand address calculated in the operand address generator is finally supplied to and stored in an bus interface circuit as an operand data. Therefore, if the operand address is not executed, an extra data remains in the bus interface circuit. As a result, an erroneous operand is executed by an instruction after the branch instruction.
In order to overcome this problem, it has been proposed that, a first signal indicating that an address to be calculated from now is an address before the branch condition is determined or decided, is generated on the basis of an execution flag of an execution unit, a branch condition information of the conditional branch instruction decoded by the instruction decoder, and an execution timing for the execution unit. The first signal thus generated is supplied together with the operand address to the bus interface circuit. In addition, after the preceding instruction before the conditional branch instruction has been executed, there is generated a second signal indicating that an instruction or instructions decoded after the branch instruction are not executed. The second signal is also supplied to the bus interface circuit.
With this arrangement, when the bus interface circuit receives the second signal, the bus interface circuit can know that the operand address supplied together with the first signal is not executed. However, before the bus interface circuit receives the second signal, the bus interface circuit starts an operation necessary for accessing the operand address. In this case, if the operand address to be accessed is not included in an associated high speed memory such as a content addressable memory or associative memory, a content of the associative memory is replaced with a different content stored in an external main memory. As a result, the branch destination instruction is stopped at the pipelined stage of the bus interface unit and the associative memory until the replacement of content of the associative memory has been completed. However, the replacement itself of content of the associative memory is not necessary, since it is no longer necessary to access the operand address supplied together with the first signal as mentioned above.
The access to the associative memory can be executed at a speed considerably higher than that of accessing to the external main memory. Therefore, when the operand access is invalid, even if the associative memory is accessed, the execution of access to the associative memory will not substantially delay execution of a succeeding instruction. However, when the operand address to be accessed is not included in the associative memory, if a bus cycle for accessing the main memory is started, a substantial time is required because access to the main memory is slow. In general, a block size of the associative memory is larger than a bus width of an external data terminal coupled to the main memory, and therefore, in order to replace the content of the associative memory, several bus cycles are required and an overhead becomes large. As a result, an substantial extra time is consumed because of the operand not to be executed, and therefore, execution of an instruction to be executed next to the conditional branch instruction is substantially delayed.